Joint IXPUG/EMEA Conference and tutorials
Ostrava, Czech Republic
March 14-18, 2016
Update: Final agenda is set! See the overall agenda of the event here. Below is the agenda of the public IXPUG part. Sessions will be held in the Sapphire Room at the Clarion Congress Hotel.
IXPUG Keynotes
- Tuesday: Joseph Curley, Senior Director, Intel Corp.: Road to Many Core & the View Ahead
- Wednesday: Chris (CJ) Newburn, Feature Architect, Intel Corp.: Bigger, faster, persistent storage and how you get to it
Schedule Overview
- Monday, beginning with a light lunch, IPCC sessions. Evening reception at the IT4Innovations Supercomputing Center
- Tuesday morning, more IPCC information, including KNL
- Tuesday afternoon, the IXPUG portion of the workshop begins
- Wednesday, IXPUG sessions
- Thursday and Friday, IXPUG tutorials
IXPUG Workshop Agenda
Tuesday, March 15
| Tuesday, March 15 | |||
| Session | Presentation | ||
| 13:30 | 14:00 | Opening | Welcome - The Intel Xeon Phi User's Group (Thomas Steinke, ZIB) |
| 14:00 | 15:00 | Keynote I | Joseph Curley (Intel): Road to Many Core & the View Ahead |
| 15:00 | 15:30 | IXPUG | Th. Steinke, G. Zitzlsberger, CJ Newburn, M. Lysaght: IXPUG Working Groups |
| 16:00 | 17:30 | Vectorization I | J. Willis, R. Bower, M. Schaller (ICC Durham): Optimisation of the core kernels of the particle-based code SWIFT on AVX and AVX2 leading to ~3x speed-up |
| L. Iapichino, F. Baruffa (LRZ Munich): Improving the vectorisation of a Gadget kernel: efficiency and potential on multiple platforms | |||
| S. Siso, L. Mason, M. Seaton (Hartree Centre, Daresbury): Code modernization of DL_MESO LBE to achieve good performance on the Intel Xeon Phi | |||
| Wednesday, March 16 | |||
| Session | Presentation | ||
| 09:00 | 10:00 | Keynote II | Chris (CJ) Newburn (Intel): Bigger, faster, persistent storage and how you get to it |
| 10:30 | 12:00 | New Application Areas | S. Muralidharan, O. Robinson, G. Civario, M. Lysaght (ICHEC, Dublin): A comparison study of vectorization approaches to optimize multiplication of large integers on Intel Xeon/Xeon Phi platforms |
| M. Ehrhardt, H. Hauswedell (FU Berlin): The SeqAn C++ library for efficient NGS sequence analysis - HPC modernisation using generic programming | |||
| M. Jaros (IT4I, Ostrava): The Fundamentals: How to accelerate Blender with the Intel Xeon Phi coprocessors | |||
| 13:00 | 14:00 | Tools | Florent Lebeau (Allinea): Experiences preparing HPC codes for Intel Knights Landing with Allinea's tools |
| 14:00 | 15:30 | Vectorization II | L. Riha, M. Merta, J. Zapletal (IT4I, Ostrava): Acceleration of FETI Solvers and the BEM4I library using the Intel Xeon Phi coprocessors |
| V. Mironov, A. Moskovsky (Lomonossov Moscow Univ.): Parallelization and optimization of Hartree-Fock method in GAMESS-US quantum chemistry code | |||
| N. Tchipev, St. Seckler, Ph. Neumann, H.-J. Bungartz (TU Munich): Optimizing ls1-mardyn for Xeon Phi | |||
| 16:00 | 18:00 | Middleware/Tools | A. Jackson, M. Weiland, N. Johnson (EPCC, Edinburgh): Power monitoring using Adept tools and RAPL |
| W.Waśko, P. Uminski, K. Kulakowski (Intel): Memkind: the API to leverage heterogeneous memory architectures | |||
| Chris (CJ) Newburn (Intel): hStreams: Easing the way to heterogeneous platforms like Knights Landing | |||
Registration
Join us in Ostrava! Register here.
Live Stream
If you can not travel to Ostrava, we offer a Live Stream. Register here.
Topics of IXPUG presentations
- Real-world workload experiences
- Optimization techniques
- Programming and runtime models
- Multi-device and multi-node scalability
- Preparing workloads for KNL
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