IXPUG Workshop at HPC Asia 2019
Date: January 14, 2019, 13:30-17:00, BallRoom C
Location: International Conference on High Performance Computing in Asia-Pacific Region, Guangzhou China at the Vanburgh Hotel. 126 Huangpu Dadao West, Guangzhou 510623, China
Registration:all attendees must register through the HPC Asia 2019 Conferencewebsite (closed post-event). The deadline for early registration is January 14, 2019 (JST). All payments must be made in Chinese Yuan (CNY).
Event Description:The Intel eXtreme Performance Users Group (IXPUG) is an active community led forum for sharing industry best practices, techniques, tools, etc. for maximizing efficiency on Intel platforms and products. IXPUG Workshop Asia 2019 is an open workship on high performance computing application, system and architectural with Intel technologies. This is a one-day workshop with two keynote talks and several contributed papers. The workshop aims to bring together software developers and technology experts to share challenges, experences and best-practice methods for the optimzation of HPC, Machine Learning and Data Analytics workloads on Intel Xeon Scalable Processors and Intel Xeon Phi Processors. The workshop will cover application performance and scalability challenges at all levels - from intra- node performace up to large-scale compute system. Any research aspect related to Intel HPC products is welcome to present in this workshop.
Call for Presentations:
IXPUG is soliciting submissions for technique presentations on innovative work using Intel architecture from users in academia, industry, government/national labs, etc. describing original discoveries, experiences and methods for obtaining efficient and scalable use of heterogeneous systems. IXPUG welcomes full paper up to 10 pages within 30mins presentaion and also welcome short paper up to 4 pages within 15mins presentation. Please submit your paper to IXPUG EasyChair. Any topics on Intel Architeture, including the following topics but not limited:
Important Dates:
Keynote Speaker: Hoon Ryu (KSIT) Biography: Dr. Hoon Ryu received B.S./M.S./Ph.D. from School of Electrical Engineering, Seoul National University / Department of Electrical Engineering, Stanford University / School of Electrical and Computer Engineering, Purdue University, respectively. He was with System LSI Division, Samsung Electronics, and currently is with Korea Institute of Science and Technology Information, where he works as a principal researcher leading Intel Parallel Computing Center. His specialty and main research interests are in simulation of advanced semiconductor devices with aids of numerical analysis coupled to high performance computing.
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Event Agenda:
Start | End | Title | Speaker |
13:30 | 13:35 | Opening Remarks | James Lin |
13:35 | 14:20 | Keynote: Massively scalable computing method for handing large eigenvalue problems for nanoelectronics modeling. | Hoon Ryu |
14:20 | 14:50 | Videl: A vision-based AI diagnoser for early leukemia | Jianwen Wei |
14:50 | 15:20 | Zhenya Song | |
15:20 | 15:40 | Coffee Break | |
15:40 | 16:00 | OpenCL-enabled high performance direct memory access for GPU-FPGA cooperative computation | Ryohei Kobayashi |
16:00 | 16:30 | Invited Talk: Introduction for benchmark test for multi-scale computional materials software | Shun Xu |
16:30 | 16:50 | Optimization of parallel mesh generation via file for multigrid method | Toshihiro Hanawa |
16:50 | 17:00 | Taisuke Boku |
Organizing Chairs
- James Lin, Shanghai Jiao Tong University
- Taisuke Boku, University of Tsukuba
Program Committee
- Doug Doerfler (NERSC/LBNL)
- Richard Gerber (NERSC/LBNL)
- Clay Hughes (SNL)
- David Keyes (KAUST)
- Kent Milfeld (TACC)
- Hai Ah Nam (LANL)
- John Pennycook (Intel)
- Thomas Steinke (Zuse Institute Berlin)
- Vit Vondrak (VSB-Technical University of Ostrava)
- Minhua Wen (Shanghai Jiao Tong Unversity)
- Yun Liang (Peking University)
- Victor Lee (Intel)
- Zhong Jin (Chinese Academic of Science)
- More to be TBD....