IXPUG Annual Conference 2025

Virtual Meeting, Hosted by TACC

Conference Dates: April 15, 2025

Location: online via Zoom, hosted by Texas Advanced Computing Center (TACC)

Registration: The event is open to all audiences, but all attendees must register: https://tacc.zoom.us/webinar/register/WN_MdU8p9JmR8Oozkk337uaBA#/registration

Event Description
IXPUG Annual Conference 2025 will shift to a one-day virtual meeting of HPC and AI experts featuring keynotes, tech talks, lightning talks, and more. The meeting will still be hosted by Texas Advanced Computing Center (TACC) but will be online via Zoom on Tuesday, April 15. The event welcomes software developers, scientists, researchers, academics, systems analysts, students, and end-users who want to share with and learn from our vibrant, global community via technical discussion and networking. Challenges surrounding application performance and scalability will be covered across all levels, including tuning and optimization of AI and HPC workloads and applications. Topics are wide-ranging, including system hardware beyond the processor (memory, interconnects, etc.) and accelerators (e.g., GPUs, AI accelerators) as well as topics related to open standards, oneAPI, software tools, programming models, OPEA, PyTorch, and more. Key themes: latest advancements in high performance computing, heterogeneous computing, artificial intelligence, visualization, memory, I/O, and storage.

Agenda

Tuesday, April 15:

All times are shown in Central Time (CT). Event details are subject to change. Registration is required.

Session 1: Chair: Amit Ruhela

09:30 - 09:40 Welcome Note – IXPUG

09:40 - 10:00 Welcome Talk & Site Update – TACC [Slides]
Presenter: Lars Koesterke, Research Associate, HPC Performance & Architectures, TACC

10:00 - 11:00 Keynote: The Evolution of Developer Software [Slides]
Presenter: Sanjiv M. Shah, Vice President in the Data Center and AI Group and General Manager of Developer Software Engineering, Intel Corporation

11:00 - 11:25 Using Low-Precision to Emulate Higher Precision for HPC
Presenter: Greg Henry, Intel Corporation

11:30 - 11:55 Joint Matrix: A Unified SYCL Extension for Matrix Hardware Programming [Slides]
Presenter: Dounia Khaldi, Intel Corporation

12:00 - 12:25 OpenMP in oneAPI: Empowering Scientific Computing on Intel Platforms, From Laptop to Aurora Exascale Supercomputer [Slides]
Presenters: Jeongnim Kim, Intel Corporation and Ye Luo, Argonne Leadership Computing Facility, Argonne National Laboratory
Co-Authors: Patrick Steinbrecher and Xinmin Tian, Intel Corporation

12:30 - 01:00 Lunch Break

Session 2: Chair: David Martin

01:00 - 01:25 Cornelis Networking Solution Deep Dive [Slides]
Presenter: Matt Williams, Field CTO, Cornelis Networks

01:30 - 01:55 SYCL Graph: Reducing Kernel Launch Overhead for Intel GPUs [Slides]
Presenter: Pablo Reble, Intel Corporation

02:00 - 02:25 Optimizing Performance in Parallel Discrete Event Simulations through Profile-Guided Partitioning [Slides]
Presenter: Sunil Reddy Maram, University of Massachusetts Dartmouth

02:30 - 02:55 Scaling Molecular Dynamics Simulations on Aurora with NAMD [Slides]
Presenter: David Hardy, University of Illinois at Urbana-Champaign
Co-Authors: Eric Bohm, University of Illinois at Urbana-Champaign; Ke Yue, Intel Corporation; Wei Jiang, Argonne National Laboratory

03:00 - 03:25 Leveraging HIP on Intel PVC [Slides]
Presenter: Brice Videau, Argonne Leadership Computing Facility, Argonne National Laboratory

03:30 - 03:55 Multi-Scale Light-Matter Dynamics in Quantum Materials on Aurora PVC [Slides]
Presenter: Nariman Piroozan, Intel Corporation
Co-Authors: Taufeq Mohammed Razakh, University of Southern California; Thomas Linker, Stanford University; Ye Luo, Argonne National Laboratory; Ken-ichi Nomura and Aiichiro Nakano, University of Southern California.

04:00 - 04:25 Wavenumber Recovery by 2D Frequency-Domain FWI from Slowness- and Source-Frequency-Limited Elastic Seismic Data [Slides]
Presenter: Sasmita Mohapatra, University of Texas at Dallas
Co-Author: George McMechan, University of Texas at Dallas

04:30 - 04:40 Quick Review, Discussions, & Closing Remarks

Important Dates (Updated)

Presenters’ confirmation and consent deadline: April 10, 2025, AoE
Final presentations due from speakers (upload to EasyChair): April 11, 2025, AoE
Conference date: April 15, 2025

Publication
IXPUG Annual Conference 2025 presentations will be published on the IXPUG website. All presenters will retain the copyright to their work.

IXPUG 2025 Program Committee

Amit Ruhela (Texas Advanced Computing Center (TACC), The University of Texas at Austin)
David Martin (Argonne Leadership Computing Facility, Argonne National Laboratory)
R. Glenn Brook (Cornelis Networks)
Steffen Christgau (Zuse Institute Berlin)
Toshihiro Hanawa (The University of Tokyo)
Clayton Hughes (Sandia National Laboratories)
Nalini Kumar (Intel Corporation)
James Lin (Shanghai Jiao Tong University)
Hatem Ltaief (King Abdullah University of Science & Technology)
Christopher Mauney (Los Alamos National Laboratory)
John Pennycook (Intel Corporation)

Submission Guidelines
If you are interested in presenting a talk, or technical session, please submit a short abstract by Friday, March 14, 2025, AoE via EasyChair. While in-person presentations are preferred, live online presentations will be allowed in exceptional cases. Published or work-in-progress research in respective areas is encouraged and presenters retain the right to publish elsewhere. All final presentations are due by April 11, 2025, AoE.

Topics of Interest

Application characterization on Intel platforms: Intel® Xeon® CPUs, Intel® Gaudi® AI accelerators, Intel GPUs, etc.), CXL-attached memory, etc.
Experiences with incorporating machine learning and deep learning in HPC applications and workflows including surrogate modeling, foundational models, augmented experiment design, etc.
Performance analysis, optimization, and best practices, and implications of HPC and HPC-AI workload behavior on system design at extreme scale (power, reliability, scalability, performance, processor design)
Memory system, I/O, interconnects (PSM2/3, OPA, ethernet)
Software environments and tools for computing at extreme scale (instrumentation, debugging/correctness, thread and process management, libraries and language development)
Experience using extreme scale systems: usability, in-situ visualization, programming challenges, algorithms and methods, etc.
Site updates from existing and forthcoming systems

Contact

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